The present invention relates to an integrated circuit viterbi decoder and a method for testing the integrated circuit viterbi decoder. More particularly, the present invention relates to the testing of the internal operations of the an integrated circuit viterbi decoder.
A viterbi decoder is used to decode an encoded convolutional code using a maximum likelihood method. The decoder selects a path of a code sequence, which is most likely to be the received code sequence, from among a plurality of known code sequences. The decoder, therefore obtains the decoded data which corresponds to the selected path. Viterbi decoders are, for example, used for error correction in satellite communication systems.
As shown in FIG. 1, a viterbi decoder comprises a distributor 1, an Adder, Comparator and Selector (ACS) circuit 2 and a path memory 3. In general, the distributor 1 calculates a branch metric based upon the demodulated output from a receiver (not shown). The ACS circuit calculates a path metric and selects a maximum likelihood path. The path memory 3 stores the selected maximum likelihood paths. A viterbi decoder is discussed in U.S. Pat. No. 4,614,933 (Ser. No. 701,504 and assigned to the same assignee as this application), and is hereby incorporated by reference.
Increasing the constraint length of a convolutional code improves the error correction capability of the verterbi decoder. But, increasing the constraint length exponentially increases the physical size of the decoder. Therefore constraint lengths are typically selected to be in the range of 3 to 4. However, even with such constraint lengths, viterbi decoder circuits are very large, and can normally only be implemented using large scale integrated circuitry.
For example, when a coding rate of 1/2 together with a constraint length of 4 are assumed, and an 8-level probablistic code signal is received, decoded output signals I and Q (FIG. 1) of the orthogonally modulated signal are, for example three bits resulting in a total of six bits being applied to the distributor 1. For each of the three bit signals applied to the distributor 1, eight possible states exist. The ACS circuit 2 comprises eight adders, comparators and selectors, with eight outputs being applied to the path memory 3.
As is known, a viterbi decoder decodes a convolutional code. Therefore, the internal conditions or states of the viterbi decoder change in dependence upon the sequence of input signals. As a result, it is extremely difficult to operationally test a viterbi decoder.
Previously, a scan-in/scan-out testing method has been to test viterbi decoders. Such a method requires that many flip-flop circuits be constructed on the LSI chip along with the viterbi decoder circuitry, in order to generate the input/output signals needed to test the viterbi decoder logic circuit. In such a method, the test results are stored in each flip-flop and are read out of the viterbi decoder integrated circuit by an external tester.
As explained above, viterbi decoder circuitry is complicated and requires a large amount of area. There is therefore no extra area for mounting such flip-flop circuits used to test the viterbi decoder in accordance with the scan-in/scan-out testing method. Consequently, it is extremely difficult to test large scale integrated circuit viterbi decoders.